This description relates to shared memory having multiple access configurations.
A system on a chip (SoC) can have multiple embedded processors in which each processor may have unique memory access timing and data bus width requirements for accessing memory. In one implementation, two embedded processors each access a separate embedded memory module according to its native access timing scheme. In another implementation, two processors having different memory access timing schemes can access a shared memory device using a bridging process. For example, suppose a first processor is designed to access memory according to a first clock frequency, a second processor is designed to access memory according to a second clock frequency, and the shared memory module is configured to be accessed according to the first clock frequency. The first processor can access the memory according to its native memory access timing scheme. The second processor can access the memory module using a bridging process in which requests are converted from the second clock domain to the first clock domain that is compatible with the memory module, and responses from the memory module are converted from the first clock domain back to the second clock domain that is compatible with the second processor.